With aggressive technology scaling accompanied by employment of new advanced materials, time-dependent di-electric breakdown (TDDB) is becoming the second leading cause of on-chip interconnect failures after electromigration (EM). In general, the TDDB is a failure mechanism of back-end-of-line interconnects (BEOL). A bridge will form between two interconnect lines when the inter-metal dielectric (IMD) breaks down as a result of long-time application of relatively low electric field. This is different from the hard break-down, which is caused by strong electric field.
The break-down is caused by formation of a conducting path through the IMD oxide between metal lines due to electron tunneling current. It leads to a significant leakage increase that degrades the circuit performance and causes the chip operation failure. Early works on TDDB have been mainly focused on the gate oxide TDDB, caused by the excessive electric fields in thin gate oxides. In contrast, TDDB in the BEOL stacks has not been a concern until recent years, due to wide dielectric spacing between metal lines and high electric strength of the inter-metal silicon dioxide.
This situation has changed with the layout feature dimensions shrink and design complexity growth. The drastically reduced wiring pitches lead to escalating electric fields between interconnects. In order to decrease the RC delay, dynamic power consumption, and cross-talk noise, porous low-k dielectric materials, with the dielectric constant k<3, have been introduced. However, the low-k materials are characterized by poor mechanical, thermal, and electrical properties in comparison with silicon dioxide. Some of the process steps such as chemical mechanical planarization (CMP) and plasma etch can potentially damage the dielectric sub-surfaces regions, generating charge carrier traps and assisting the conduction. As a result, the integrated circuit chips integrated with the copper/low-k interconnects tend to be vulnerable to TDDB failure.
Great efforts have been made to model TDDB degradation. These proposed field acceleration models are based on different TDDB mechanisms. There is no universal agreement among them and the underlying physics of the dielectric breakdown is still not completely defined. The frequently-employed thermochemical E-model (J. McPherson and H. Mogul, “Underlying Physics of the Thermochemical E Model in Describing Low-Field Time-Dependent Dielectric Breakdown in SiO2 Thin Films,” Journal of Applied Physics, vol. 84, no. 3, pp. 1513-1523, 1998) and 1/E-model (I. C. Chen, S. Holland, and C. Hu, “A Quantitative Physical Model for Time-Dependent Breakdown in SiO2,” in IEEE International Reliability Physics Symposium (IRPS), pp. 26-28, 1985.) were initially developed for gate oxides. The E-model describes weak bond breakage due to thermochemical heating while the 1/E-model refers to high energy hole injection induced damage. These models were later examined toward extension on the copper/low-k interconnect TDDB. The major difference between TDDB in low-k BEOL dielectrics and gate oxides is the presence of metal ions in the former interior.
The √{square root over (E)}-model, first proposed for metal-SiN-metal capacitors, has been employed for the low-k TDDB, assuming that the copper ions play a major role in dielectric breakdown. (F. Chen et al., “A Comprehensive Study of Low-k SiCOH TDDB Phenomena and Its Reliability Lifetime Model Development,” in IEEE International Reliability Physics Symposium (IRPS), pp. 46-53, 2006; and N. Suzumura et al., “A New TDDB Degradation Model Based on Cu Ion Drift in Cu Interconnect Dielectrics,” in IEEE International Reliability Physics Symposium (IRPS), pp. 26-30, 2006). Lately, experimental data collected at the low fields have demonstrated the overly conservative predictions generated by the E and √{square root over (E)} models, and too optimistic predictions with the 1/E model. (J. W. McPherson, “Time Dependent Dielectric Breakdown Physics-Models Revisited,” Microelectronics Reliability, vol. 52, no. 9, pp. 1753-1760, 2012). In addition, even though the break-down event depends on the formation of the conducting path of traps connecting the two electrodes (metal lines), all proposed TDDB models fail to describe the kinetics of conduction path generation. Majority of currently employed TDDB assessment approaches are based on calculations of the across-layout electrostatic fields and, thus, cannot provide any kind of the interconnect lifetime assessment.
A robust full-chip assessment technique for low-k TDDB is needed for evaluating the amount of the inter-metal dielectric degradation measured by the leakage current density and the mean time to failure during the circuit design. The copper/low-k dielectric structures are characterized by a wide variety of geometries. The architecture of a metal line, which includes the capping (etch stop) layer 310 and the diffusion barrier 320 coating the copper bulk as shown in FIG. 3, may impact the TDDB-induced interconnect lifetime. Distribution of the electric field in inter-metal dielectric gaps affects both the kinetics of the current conducting path generation and the resulting leakage current density. One method (Bashir et al., “Backend Low-k TDDB Chip Reliability Simulator,” in IEEE International Reliability Physics Symposium (IRPS), pp. 2C.2.1-2C.2.10, 2011.), assumes a fixed voltage drop between all neighboring metal segments in the proposed full-chip TDDB simulator. However, interconnects in the chip can be categorized as power/ground lines and signal lines. Patterns with the same geometries but different power/ground/signal line combinations, e.g. with the different electric loads, will be characterized by different TDDB activities. Thus, this method can lead to too conservative results. Moreover, this method uses only a general formula to model the system lifetime. Novel solutions should be developed to mitigate the mentioned problems for full-chip TDDB assessment.